Investigation of InxGa1−xAs Ultra-Thin-Body Tunneling FETs using a Full-Band and Atomistic Approach Mathieu Luisier and Gerhard Klimeck Network for Computational Nanotechnology, Purdue University, 465 Northwestern Ave, West Lafayette, IN 47907, USA / e-mail: firstname.lastname@example.org Abstract—Using a 2-D, full-band, atomistic, quantum mechanical simulator based on the sp3 d5 s∗ tight-binding method with spin-orbit coupling, we investigate the performances of singleand double-gate relaxed Inx Ga1−x As p − i − n ultra-thin-body (UTB) tunneling field-effect transistors (TFETs) with 20nm to 50nm gate lengths. The ON-current, OFF-current leakage, and subthreshold slope (SS) properties are analyzed as function of the In concentration in 5nm thick structures. We find (i) that devices with a high In concentration allow more ON-current, but suffer from higher OFF-currents and lower SS, (ii) that doublegate devices perform better than single-gate ones, and (iii) that a longer gate length reduces the source-to-drain tunneling leakage and the OFF-current of the UTB TFETs. I. I NTRODUCTION Tunneling field-effect transistors (TFETs) are expected to help reduce the power consumption of integrated circuits due to their potential low OFF-currents and subthreshold swing (SS) below 60 mV/dec at room temperature . In effect the voltage swing required to switch TFETs from their OFF to their ON state is not limited by thermionic emission as in conventional MOSFETs, but depends on the band-to-band tunneling probability of valence band electrons, so that SS can go below 60 mV/dec. Recent experimental works have shown that TFETs with a SS lower than 60 mV/dec can be realized using either carbone nanotube or silicon-on-insulator structures , . A SS of 40 mV/dec and 52.8 mV/dec were reported, respectively. However, both devices exhibit low ON-currents so that alternative channel materials, such as graphene nanoribbons , Si/SiGe heterostructures , or III-V compound semiconductors , are investigated to increase the ON-current. The small electron and hole effective masses of InAs or GaAs could enable large band-to-band tunneling in properly designed p − i − n transistor structures. Computer aided design can help reduce the fabrication costs of such devices. For that purpose we use a quantum mechanical simulation tool that goes beyond the Wentzel-Kramers-Brillouin (WKB) approximation that is essentially one-dimensional and ignores quantization and confinement effects. Hence, we present a 2-D, atomistic, full-band study of single- (SG) and doublegate (DG) p − i − n ultra-thin-body TFETs based on relaxed Inx Ga1−x As with an indium concentration x ranging from 0 to 1. We demonstrate under which conditions these devices could offer large ON-currents and steep SS. II. M ETHOD We have developed an atomistic, full-band quantum transport simulator based on the nearest neighbor sp3 d5 s∗ tightbinding method with spin-orbit coupling and self-consistent solutions of 2-D Schr¨odinger and Poisson equations. In the case of ballistic transport we use a Wave Function (WF) approach which is numerically identical to the Non-equilibrium Green’s Function (NEGF) formalism, but computationally much more efficient . It consists in solving sparse linear systems of equations “Ax=b” instead of matrix inversion problems as in NEGF. Each atom composing the active region of the simulation domain is represented by a matrix of size tB =20. The total Hamiltonian matrix is then block tri-diagonal with sparse blocks whose size depends on the number of atoms in each atomic layer. The insulator layers that separate the III-V channel from the gate contacts do not participate to the transport calculation, are modeled as fictitious materials with an infinite band gap, and are solely characterized by their relative dielectric constant ǫR in the Poisson equation. Carrier and current densities are obtained by injecting electrons and holes into the device structures from the source and drain contacts at different energies and wave vectors. The calculation of the electrostatic potential is self-consistently coupled to that of the charge density. Electrons that tunnel from the valence band of the p-doped side of the device into the conduction band of the n-doped side contribute to both the current and charge densities. The solution of Schr¨odinger and Poisson equations are massively parallelized to reduce the simulation time . Our tool models quantization effects as well as the valence and conduction bands of various semiconductor materials simultaneously. The band gap and effective masses of InAs and GaAs are correctly reproduced only if spin-orbit coupling is included in the calculation. The neglection of this effect leads to an increase of the band gap and of the electron effective mass so that the band-to-band tunneling probability is underestimated. Furthermore, the tight-binding model automatically accounts for the imaginary band dispersion that exists in the energy band gap. Band-to-band tunneling processes are therefore accurately modeled for direct gap materials even in the InAs -5.5004 4.1511 -0.5819 6.9716 19.7106 19.9414 13.0317 13.3071 -1.6944 -4.2104 -2.4267 -1.1599 2.5982 2.8094 2.0677 0.9373 -2.2684 -2.2931 -0.8994 -0.4890 4.3106 -1.2890 -1.7314 -1.9784 2.1889 2.4560 -1.5846 2.7179 -0.5051 0.1723 0.1312 BInAs GaAs 0.0 0.0 -0.2040 0.2621 0.0 -1.4772 0.0 0.3427 -0.0262 -0.2850 -0.0545 -0.1022 -0.0667 -0.1488 0.0911 -0.0902 0.3152 -0.0131 -0.2711 0.3556 -0.1355 0.1185 0.1210 0.0876 -0.0979 -0.0931 0.0327 0.2117 0.3464 0.0 0.0 1.6 1 0.8 0.6 0.4 InAs 0.2 0 0.4 0.6 0.8 1 Fig. 1. Band gap of Inx Ga1−x As at room temperature as function of the In concentration x. The solid line is the analytical model from Ref. , the dots the results from tight-binding with the bowing parameters in Fig. I, while the bowing parameters are ignored to obtain the dashed line (only linear interpolation of the InAs and GaAs parameters). 0.07 0.06 Analytical Model Tight−Binding (with Bowing) Tight−Binding (without Bowing) GaAs 0.05 0.04 0.03 0.02 0 absence of scattering. InAs 0.2 0.4 0.6 0.8 1 x III. PARAMETRIZATION Tight-binding parameters for InAs and Gas can be found in the literature , but there is no specific parameters for relaxed InxGa1−x As. As a first approximation, the InAs and GaAs parameters can be linearly interpolated to obtain InGaAs. The band gap and effective masses are not correctly reproduced in this case as pointed out in Ref.  and shown in Fig. 1 and 2. A better description of Inx Ga1−x As is possible by introducing bowing parameters BInAs GaAs for each onsite and two-center integral tight-binding parameters x · PInAs + (1 − x) · PGaAs + x · (1 − x) · BInAs 0.2 x FOURTH COLUMN CONTAINS THE REQUIRED BOWING PARAMETERS BInAs GaAs TO OBTAIN I N G A A S . A LL PARAMETERS ARE IN EV. = GaAs 1.2 TABLE I T IGHT- BINDING DIAGONAL , SPIN - ORBIT, AND TWO - CENTER INTEGRAL PARAMETERS FOR G A A S AND I N A S ( BOTH TAKEN FROM R EF. ). T HE PInx Ga1−x As Analytical Model Tight−Binding (with Bowing) Tight−Binding (without Bowing) 1.4 Eg (eV) GaAs -5.5004 4.1511 -0.2412 6.7078 19.7106 22.6635 13.0317 12.7485 -1.6451 -3.6772 -2.2078 -1.3149 2.6649 2.9603 1.9765 1.0275 -2.5836 -2.3206 -0.6282 -0.1332 4.1508 -1.4274 -1.8743 -1.8896 2.5293 2.5491 -1.2700 2.5054 -0.8517 0.1723 0.0218 Electron Effective Mass Parameter Esa Epa Esc Epc Es∗a Es∗c Eda Edc ssσ s∗ s∗ σ s∗a sc σ sa s∗c σ sa p c σ sc p a σ s∗a pc σ s∗c pa σ sa dc σ sc da σ s∗a dc σ s∗c da σ ppσ ppπ p a dc σ p c da σ p a dc π p c da π ddσ ddπ ddδ λa λc GaAs . (1) The values of the different BInAs GaAs are listed in Table I and are optimized to ensure the correct reproduction of the widely accepted band gaps and effective masses of the ternary alloys  as illustrated in Fig. 1 and 2. Hence, no atomic disorder is taken into account in this work. In fitting the BInAs GaAs we impose the condition that the parameters PInx Ga1−x As are larger than the minimum of Fig. 2. Electron effective mass of Inx Ga1−x As at room temperature as function of the In concentration x. The same plotting convention as in Fig. 1 are used. PInAs and PGaAs and smaller than the maximum of PInAs and PGaAs for all the values of x . IV. R ESULTS We consider single- and double-gate InxGa1−x As p − i − n ultra-thin-body (UTB) TFETs structures as depicted in Fig. 3. The source and drain regions measure 20nm and are highly doped with a concentration NA =5e19 cm−3 and ND =5e19 cm−3 , respectively. The body thickness tbody is set to 5nm, the insulator layer separating the gate from the channel to tox =1nm with a relative dielectric constant ǫR =12.7. The transport direction of the channel is aligned with the <100> crystal axis, the surface orientation is along (100). We start with a gate length of Lg =20nm to attempt to fulfill the future ITRS requirement. The number of atoms taken into 120 Single Gate Double Gate tox (a) tbody (b) Lg Fig. 3. TFET structures. (a) Single-Gate and (b) Double-Gate p − i − n UTBs with tbody =5nm, tox =1nm, and 20nm long p-doped (NA =5e19 cm−3 ) source and n-doped (ND =5e19 cm−3 ) drain extensions. c 4 SS=115 mV/dec SS 0 c de c V/ /de mV −4 28 10 5m 6 S= S SS = d I (µA/µm) 10 =5 0m V/ de 10 10 10 −8 SG GaAs DG GaAs SG InAs DG InAs −12 −0.5 0 Vgs (V) 0.5 Fig. 4. Transfer characteristics Id − Vgs at Vds =0.2 V of GaAs and InAs single- and double-gate TFETs with a gate length Lg =20nm. The subthreshold swing SS of the four TFETs is reported. account in the Schr¨odinger equation ranges from 6732 for the InAs structure to 7632 for the GaAs TFET resulting in Hamiltonian matrices of size 134640 and 152640, respectively. Single-gate structures are easier to manufacture than doublegate ones. However, due to a poorer electrostatic control , they exhibit larger SS, more than 60 mV/dec, and lower ONcurrents than DG devices as can be seen from Fig. 4 to Fig. 7, Subthreshold Swing (mV/dec) tbody tox Lg 100 80 60 mV/dec 60 40 20 0 0.25 0.53 In Concentration 0.75 1 Fig. 5. Subthreshold swing SS of single- (dashed line with symbols) and double-gate (solid line) Inx Ga1−x As TFETs with an indium concentration ranging from x=0 to x=1 and Lg =20nm. irrespective of the indium concentration in the channel. The poor SS of SG TFETs is mainly due to source-to-drain tunneling (STDT) leakage through the gate potential barrier as indicated in Fig. 7. This effect is almost suppressed by a better electrostatic control in DG TFETs that makes the source-todrain barrier effectively longer than in SG TFETs. It results SS values ranging from 28 mV/dec for GaAs to 50 mV/dec for InAs as compared to 65 mV/dec and 115 mV/dec in SG devices. The larger ON-current of DG TFETs is also a consequence of the better electrostatic control provided by two gates instead of a single one. The electric field at the p−i interface becomes larger in DG structures so that the width of the tunneling barrier decreases and electrons can more efficiently flow from the valence band of the source to the conduction band of the drain as shown in Fig. 7. The channels with a smaller indium concentration suffer less from STDT leakage and have steeper SS because of their higher band gap and larger tunneling effective mass, but they are characterized by lower ON-currents for the same two reasons. Since a high ON-current is desired, InAs-based devices should be promoted. They can reach ON-currents in the order of 130 and 210 µA/µm for SG and DG, respectively. Note that such ON-current values can only be achieved if the gate voltage swing from the OFF to the ON transistor state amounts to about 0.4 V while the supply voltage VDD and the drain-to-source voltage Vds are set to 0.2 V. Increasing Vds to 0.4 V is not an appropriate solution since Vbi +Vds the built-in potential of the p − i − n diode plus the drain-tosource voltage becomes larger than 2·Eg (2 times the band gap of the channel), which causes large OFF-current and strongly increases the ambipolar behavior of the TFETs . Simultaneously reducing the doping of the n-doped drain and increasing Vds appears more promising. Also, to avoid the fabrication complexity of DG structures 3 1.5 10 Single Gate Double Gate 2 1 VB Edge Energy (eV) 1 10 0 10 0.5 CB Edge 0 −0.5 −1 10 −1 0 −2 0.25 0.53 In Concentration 0.75 1 Fig. 6. ON-current (Id at Vgs =0.6 V and Vds =0.2 V) of single- and doublegate (solid line) Inx Ga1−x As TFETs. Same label conventions as in Fig. 5. while minimizing SS the gate length of single-gate InAs devices can be extended to 40nm. At this size STDT completely disappears as SS becomes independent of the gate length as shown in Fig. 8. However, increasing the gate length of devices that might play a role in 2 to 5 years goes in the opposite direction of the ITRS requirement. V. C ONCLUSION Ultra-thin-body Inx Ga1−x As TFETs with single- and double-gate configurations have been modeled with a full atomistic device simulation tool. We have found that (1) DG structures offer higher ON-current and steeper SS, (2) SS improves with decreasing indium concentration in the channel while ON-current follows the opposite trend, and (3) SS can be reduced by increasing the gate length of InAs SG FETs. However, the replacement of conventional Si MOSFETs by III-V TFETs will only be achieved if the TFET ON-current can further be increased by design optimization like the doping of the p, i, and n regions, by introducing gate under- or overlap, or by including heterostructures. ACKNOWLEDGMENT This work was partially supported by NSF grant EEC0228390 that funds the Network for Computational Nanotechnology, by NSF PetaApps grant number 0749140, by the Nanoelectronics Research Initiative through the Midwest Institute for Nanoelectronics Discovery, and by NSF through TeraGrid resources provided by the National Institute for Computational Sciences (NICS). R EFERENCES  Q. Zhang, W. Zhao and, A. Seabaugh, IEEE Elec. Dev. Lett., 27, p. 297, 2006.  J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, Phys. Rev. Lett. 93, 196805, 2004.  W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, IEEE Elec. Dev. Lett., 28, p. 743, 2007. p+ 10 intrinsic 20 30 x (nm) 40 n+ 50 60 Fig. 7. Conduction and valence band edges of a single- (solid lines) and double-gate (dashed lines) InAs TFET along its transport direction at Vds =0.2 V and Vgs =-0.3 V. The leakage path of the tunneling current through the gate potential barrier is indicated. 150 Subthreshold Swing (mV/dec) 0 Leakage 150 I ON 100 125 60 mV/dec 50 ON Current (µA/µm) ON Current (µA/µm) 10 10 Single Gate Double Gate SS 0 20 25 30 35 40 Gate Length (nm) 45 100 50 Fig. 8. Subthreshold swing (left axis, solid line) and ON-current (right axis, dashed line with symbols) of single-gate InAs TFETs with gate lengths Lg comprised between 20nm and 50nm.  Q. Zhang, T. Fang, H. Xing, A. Seabaugh, and D. Jena, IEEE Elec. Dev. Lett., 29, p. 1344, 2008.  K. K. Bhuwalka, J. Schulze, and I. Eisele, Jpn. J. Appl. Phys., 43, p. 4073, 2004.  M. Luisier and G. Klimeck, IEEE Elec. Dev. Lett., 30, p. 602, 2009.  J. Knoch, S. Mantl and J. Appenzeller, Solid-State Electronics, 51, p. 572, 2007.  M. Luisier, G. Klimeck, A. Schenk, and W. Fichtner, Phys. Rev. B, 74, 205323, 2006.  M. Luisier and G. Klimeck, Proceedings of the 2008 ACM/IEEE conference on Supercomputing, article 12, 2008.  T. B. Boykin, G. Klimeck, R. Chris Bowen, and F. Oyafuso, Phys. Rev. B, 66, 125207, 2002.  T. B. Boykin, M. Luisier, A. Schenk, N. Kharche, and G. Klimeck, IEEE Trans. on Nanotechnology, 6, p. 43, 2007.  http://www.ioffe.rssi.ru/SVA/NSM/Semicond/  T. B. Boykin, private communication, 2008.
1454773287_83f3b7da85 doc417_luiseri_sispad_final. https://engineering.purdue.edu/gekcogrp/publications/pubs_src/DOC417_Luiseri_sispad_final.pdf https://engineering.purdue.edu/gekcogrp/publications/pubs_src/DOC417_Luiseri_sispad_final.pdf 2016-02-06 16:41:27 http://Correctgaming.Com/5314445.html#doc417_luiseri_sispad_final. http://Correctgaming.Com/1454773287_83f3b7da85.html#doc417_luiseri_sispad_final. http://Correctgaming.Com/cracker/1454773287_83f3b7da85/doc417_luiseri_sispad_final.pdf http://Correctgaming.Com/cracker/1454773287_83f3b7da85/doc417_luiseri_sispad_final.txt
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